{"id":9978,"date":"2026-08-10T10:13:36","date_gmt":"2026-08-10T10:13:36","guid":{"rendered":"https:\/\/nokobox.com\/index.php\/item\/udemy-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf-2025-4\/"},"modified":"2026-08-10T10:13:36","modified_gmt":"2026-08-10T10:13:36","slug":"udemy-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf-2025-4","status":"publish","type":"digital_item","link":"https:\/\/nokobox.com\/index.php\/item\/udemy-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf-2025-4\/","title":{"rendered":"Udemy \u2013 VLSI\/FPGA Resume Project: 2D DMA Controller with APB+AXI Inf 2025-4"},"content":{"rendered":"<div class=\"w-post-elm post_content\">\n<h2><span style=\"vertical-align: inherit\">Description<\/span><\/h2>\n<p><span style=\"vertical-align: inherit\">VLSI\/FPGA Resume Project: 2D DMA Controller with APB+AXI Inf. This comprehensive course guides participants through the design process of a complex and functional IP block called a 2D DMA Controller. The design portion of this project is expected to consist of over 2000 lines of Verilog code. In addition to the design, a practical example of this IP block will be presented: running the 2D Plants Vs. Zombies game on the Zynq7010 FPGA platform. Using this powerful DMA controller, it is possible to build a variety of 2D games, and the main limitation in this area will be the software development efforts.<\/span><\/p>\n<div data-purpose=\"safely-set-inner-html:description:description\">\n<p data-sourcepos=\"7:1-7:493\"><span style=\"vertical-align: inherit\">Successful completion of this project can give participants a significant advantage over other applicants for related jobs and teach them the skills needed to design other complex IP blocks. This 2D DMA controller is feature-rich and has APB3 and AXI4 interfaces. The controller is specifically designed for image and video processing applications, while also being compatible with traditional 1D DMA controllers.<\/span><\/p>\n<h3 data-sourcepos=\"23:1-23:24\"><strong><span style=\"vertical-align: inherit\">What you will learn<\/span><\/strong><\/h3>\n<ul data-sourcepos=\"25:1-34:0\">\n<li data-sourcepos=\"25:1-25:47\"><span style=\"vertical-align: inherit\">Complete IP design process from specification to design synthesis.<\/span><\/li>\n<li data-sourcepos=\"26:1-26:49\"><span style=\"vertical-align: inherit\">Learn to design complex IP blocks independently.<\/span><\/li>\n<li data-sourcepos=\"27:1-27:19\"><span style=\"vertical-align: inherit\">DMA performance concept.<\/span><\/li>\n<li data-sourcepos=\"28:1-28:34\"><span style=\"vertical-align: inherit\">Two-dimensional DMA controller design specifications.<\/span><\/li>\n<li data-sourcepos=\"29:1-29:25\"><span style=\"vertical-align: inherit\">Hardware architecture analysis.<\/span><\/li>\n<li data-sourcepos=\"30:1-30:24\"><span style=\"vertical-align: inherit\">Line-by-line review of RTL code.<\/span><\/li>\n<li data-sourcepos=\"31:1-31:36\"><span style=\"vertical-align: inherit\">Behavioral model of Slave AXI and Master APB.<\/span><\/li>\n<li data-sourcepos=\"32:1-32:23\"><span style=\"vertical-align: inherit\">Complex IP verification environment.<\/span><\/li>\n<li data-sourcepos=\"33:1-34:0\"><span style=\"vertical-align: inherit\">A complete Zynq-based FPGA project that implements the Plants Vs. Zombies game using your own designed IP.<\/span><\/li>\n<\/ul>\n<h3 data-sourcepos=\"35:1-35:30\"><strong><span style=\"vertical-align: inherit\">This course is suitable for people who:<\/span><\/strong><\/h3>\n<ul data-sourcepos=\"37:1-38:64\">\n<li data-sourcepos=\"37:1-37:74\"><span style=\"vertical-align: inherit\">Graduate students seeking a career in VLSI\/FPGA design.<\/span><\/li>\n<li data-sourcepos=\"38:1-38:64\"><span style=\"vertical-align: inherit\">Engineers who wish to improve their VLSI\/FPGA design skills.<\/span><\/li>\n<\/ul>\n<\/div>\n<h3><span style=\"vertical-align: inherit\">Course Description VLSI\/FPGA Resume Project: 2D DMA Controller with APB+AXI Inf<\/span><\/h3>\n<ul>\n<li><span style=\"vertical-align: inherit\">Publisher:&nbsp; <\/span><a href=\"https:\/\/href.li\/?https:\/\/www.udemy.com\/course\/vlsifpga-resume-project-2d-dma-controller-with-apbaxi-inf\/\" target=\"_blank\" rel=\"noopener\"><span style=\"vertical-align: inherit\">Udemy<\/span><\/a><\/li>\n<li><span style=\"vertical-align: inherit\">Instructor:&nbsp; <\/span><a class=\"ud-btn ud-btn-medium ud-btn-link ud-heading-sm ud-text-sm ud-instructor-links\" href=\"https:\/\/downloadlynet.ir\/tag\/sky-siliconthink\/\" data-position=\"1\"><span class=\"ud-btn-label\"><span style=\"vertical-align: inherit\">SKY SiliconThink<\/span><\/span><\/a><\/li>\n<li><span style=\"vertical-align: inherit\">Training level: Beginner to advanced<\/span><\/li>\n<li><span style=\"vertical-align: inherit\">Training duration: 7 hours and 6 minutes<\/span><\/li>\n<li><span style=\"vertical-align: inherit\">Number of lessons: 48<\/span><\/li>\n<\/ul>\n<h3><span style=\"vertical-align: inherit\">Course headings<\/span><\/h3>\n<h2>&nbsp;<img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-980219 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2025\/04\/VLSI-FPGA-Resume-Project-2D-DMA-Controller-with-APBAXI-Inf-12.png\" alt=\"VLSI\/FPGA Resume Project: 2D DMA Controller with APB+AXI Inf\" width=\"790\" height=\"687\"><\/h2>\n<h3><span style=\"vertical-align: inherit\">Prerequisites for the VLSI\/FPGA Resume Project: 2D DMA Controller with APB+AXI Inf course<\/span><\/h3>\n<div class=\"ud-block-list-item ud-block-list-item-small ud-block-list-item-tight ud-block-list-item-neutral ud-text-sm\">\n<ul>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Digital Fundamentals<\/span><\/li>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Verilog<\/span><\/li>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">APB3\/AXI4 Bus Protocol<\/span><\/li>\n<\/ul>\n<\/div>\n<h3><span style=\"vertical-align: inherit\">Course images<\/span><\/h3>\n<h2><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-980218 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2025\/04\/VLSI-FPGA-Resume-Project-2D-DMA-Controller-with-APBAXI-Inf.png\" alt=\"VLSI\/FPGA Resume Project: 2D DMA Controller with APB+AXI Inf\" width=\"723\" height=\"366\"><\/h2>\n<h3><span style=\"vertical-align: inherit\">Sample course video<\/span><\/h3>\n<div style=\"width: 640px;\" class=\"wp-video\"><span class=\"mejs-offscreen\">Video Player<\/span><\/p>\n<div id=\"mep_0\" class=\"mejs-container mejs-container-keyboard-inactive wp-video-shortcode mejs-video\" tabindex=\"0\" role=\"application\" aria-label=\"Video Player\" style=\"width: 640px; height: 360px; min-width: 217px;\">\n<div class=\"mejs-inner\">\n<div class=\"mejs-mediaelement\"><mediaelementwrapper id=\"video-162624-1\"><video class=\"wp-video-shortcode\" id=\"video-162624-1_html5\" width=\"640\" height=\"360\" preload=\"metadata\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_Downloadly.ir.mp4?_=1\" style=\"width: 640px; height: 360px;\"><source type=\"video\/mp4\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_Downloadly.ir.mp4?_=1\"><a href=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_Downloadly.ir.mp4?nocache=1786136803687\">https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_Downloadly.ir.mp4<\/a><\/video><\/mediaelementwrapper><\/div>\n<div class=\"mejs-layers\">\n<div class=\"mejs-poster mejs-layer\" style=\"display: none; width: 100%; height: 100%;\"><\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-loading\"><span class=\"mejs-overlay-loading-bg-img\"><\/span><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-error\"><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer mejs-overlay-play\" style=\"width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-button\" role=\"button\" tabindex=\"0\" aria-label=\"Play\" aria-pressed=\"false\"><\/div>\n<\/div>\n<\/div>\n<div class=\"mejs-controls\">\n<div class=\"mejs-button mejs-playpause-button mejs-play\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Play\" aria-label=\"Play\" tabindex=\"0\"><\/button><\/div>\n<div class=\"mejs-time mejs-currenttime-container\" role=\"timer\" aria-live=\"off\"><span class=\"mejs-currenttime\">00:00<\/span><\/div>\n<div class=\"mejs-time-rail\"><span class=\"mejs-time-total mejs-time-slider\" role=\"slider\" tabindex=\"0\" aria-label=\"Time Slider\" aria-valuemin=\"0\" aria-valuemax=\"0\" aria-valuenow=\"0\" aria-valuetext=\"00:00\"><span class=\"mejs-time-buffering\" style=\"display: none;\"><\/span><span class=\"mejs-time-loaded\"><\/span><span class=\"mejs-time-current\"><\/span><span class=\"mejs-time-hovered no-hover\"><\/span><span class=\"mejs-time-handle\"><span class=\"mejs-time-handle-content\"><\/span><\/span><span class=\"mejs-time-float\"><span class=\"mejs-time-float-current\">00:00<\/span><span class=\"mejs-time-float-corner\"><\/span><\/span><\/span><\/div>\n<div class=\"mejs-time mejs-duration-container\"><span class=\"mejs-duration\">00:00<\/span><\/div>\n<div class=\"mejs-button mejs-volume-button mejs-mute\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Mute\" aria-label=\"Mute\" tabindex=\"0\"><\/button><a href=\"javascript:void(0);\" class=\"mejs-volume-slider\" aria-label=\"Volume Slider\" aria-valuemin=\"0\" aria-valuemax=\"100\" role=\"slider\" aria-orientation=\"vertical\"><span class=\"mejs-offscreen\">Use Up\/Down Arrow keys to increase or decrease volume.<\/span><\/p>\n<div class=\"mejs-volume-total\">\n<div class=\"mejs-volume-current\" style=\"bottom: 0px; height: 100%;\"><\/div>\n<div class=\"mejs-volume-handle\" style=\"bottom: 100%; margin-bottom: -3px;\"><\/div>\n<\/div>\n<p><\/a><\/div>\n<div class=\"mejs-button mejs-fullscreen-button\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Fullscreen\" aria-label=\"Fullscreen\" tabindex=\"0\"><\/button><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div>\n<h3><span style=\"vertical-align: inherit\">Installation Guide<\/span><\/h3>\n<p><span style=\"vertical-align: inherit\">After Extract, view with your favorite player.<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Subtitles: None<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Quality: 720p<\/span><\/p>\n<\/div>\n<h3><span style=\"vertical-align: inherit\">Download link<\/span><\/h3>\n<p><a href=\"https:\/\/dl3.downloadly.ir\/Files\/Elearning\/Udemy_VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_2025-4.part1_Downloadly.ir.rar?nocache=1786136802\"><span style=\"vertical-align: inherit\">Download Part 1 \u2013 1 GB<\/span><\/a><\/p>\n<p><a href=\"https:\/\/dl3.downloadly.ir\/Files\/Elearning\/Udemy_VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_2025-4.part2_Downloadly.ir.rar?nocache=1786136802\"><span style=\"vertical-align: inherit\">Download Part 2 \u2013 1 GB<\/span><\/a><\/p>\n<p><a href=\"https:\/\/dl3.downloadly.ir\/Files\/Elearning\/Udemy_VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_2025-4.part3_Downloadly.ir.rar?nocache=1786136802\"><span style=\"vertical-align: inherit\">Download Part 3 \u2013 1 GB<\/span><\/a><\/p>\n<p><a href=\"https:\/\/dl3.downloadly.ir\/Files\/Elearning\/Udemy_VLSIFPGA_Resume_Project_2D_DMA_Controller_with_APB_AXI_Inf_2025-4.part4_Downloadly.ir.rar?nocache=1786136802\"><span style=\"vertical-align: inherit\">Download Part 4 \u2013 409 MB<\/span><\/a><\/p>\n<p><span style=\"vertical-align: inherit\">File(s) password: www.downloadly.ir<\/span><\/p>\n<h3><span style=\"vertical-align: inherit\">File size<\/span><\/h3>\n<p><span style=\"vertical-align: inherit\">3.4 GB<\/span><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Description VLSI\/FPGA Resume Project: 2D DMA Controller with APB+AXI Inf. This comprehensive course guides participants through the design process of a complex <\/p>\n","protected":false},"author":1,"template":"","dgi_category":[10458],"dgi_tag":[85171,85172,85173,85174,85175,85170],"class_list":["post-9978","digital_item","type-digital_item","status-publish","has-post-thumbnail","hentry","dgi_category-video-tutorials","dgi_tag-course-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf","dgi_tag-download-course-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf","dgi_tag-download-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf","dgi_tag-free-download-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf","dgi_tag-free-vlsi-fpga-resume-project-2d-dma-controller-with-apbaxi-inf","dgi_tag-sky-siliconthink"],"_links":{"self":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/9978","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item"}],"about":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/types\/digital_item"}],"author":[{"embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"version-history":[{"count":0,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/9978\/revisions"}],"wp:attachment":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/media?parent=9978"}],"wp:term":[{"taxonomy":"dgi_category","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_category?post=9978"},{"taxonomy":"dgi_tag","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_tag?post=9978"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}