{"id":8861,"date":"2026-08-10T10:00:47","date_gmt":"2026-08-10T10:00:47","guid":{"rendered":"https:\/\/nokobox.com\/index.php\/item\/udemy-asic-verification-using-system-verilog-sv-project-demo-2025-7\/"},"modified":"2026-08-10T10:00:47","modified_gmt":"2026-08-10T10:00:47","slug":"udemy-asic-verification-using-system-verilog-sv-project-demo-2025-7","status":"publish","type":"digital_item","link":"https:\/\/nokobox.com\/index.php\/item\/udemy-asic-verification-using-system-verilog-sv-project-demo-2025-7\/","title":{"rendered":"Udemy \u2013 ASIC Verification using System Verilog (SV) + Project Demo 2025-7"},"content":{"rendered":"<div class=\"w-post-elm post_content\">\n<p>&nbsp;<\/p>\n<h2><span style=\"vertical-align: inherit\">Description<\/span><\/h2>\n<p><span style=\"vertical-align: inherit\">IP Verification using System Verilog (SV) with Project Demo course. This course is designed for beginners to experts. The content of this System Verilog course is structured in such a way that participants can learn and practice the modules in a few weeks.<\/span><\/p>\n<p data-sourcepos=\"30:1-30:363\"><span style=\"vertical-align: inherit\">During the course, various example codes are explained and a number of applications are simulated in industry standard simulators. Also, an example protocol is selected and testbench code is developed for it and test cases are written for the project. The assignments provided help the participants to practice writing the code and use it to develop the test bench and test cases.<\/span><\/p>\n<h3 data-sourcepos=\"32:1-32:24\"><strong><span style=\"vertical-align: inherit\">What you will learn<\/span><\/strong><\/h3>\n<ul data-sourcepos=\"34:1-38:0\">\n<li data-sourcepos=\"34:1-34:24\"><span style=\"vertical-align: inherit\">IP Verification Concepts<\/span><\/li>\n<li data-sourcepos=\"35:1-35:47\"><span style=\"vertical-align: inherit\">Learning System Verilog language for Verification<\/span><\/li>\n<li data-sourcepos=\"36:1-36:85\"><span style=\"vertical-align: inherit\">Develop test bench and test cases based on System Verilog to verify a specific IP<\/span><\/li>\n<li data-sourcepos=\"37:1-38:0\"><span style=\"vertical-align: inherit\">A case study: How to verify an IP using SV<\/span><\/li>\n<\/ul>\n<h3 data-sourcepos=\"39:1-39:32\"><strong><span style=\"vertical-align: inherit\">This course is suitable for people who:<\/span><\/strong><\/h3>\n<ul data-sourcepos=\"41:1-42:44\">\n<li data-sourcepos=\"41:1-41:50\"><span style=\"vertical-align: inherit\">Internship for BE\/MTech (ECE, EEE) students<\/span><\/li>\n<li data-sourcepos=\"42:1-42:44\"><span style=\"vertical-align: inherit\">Engineers who are new to System Verilog.<\/span><\/li>\n<\/ul>\n<div data-purpose=\"safely-set-inner-html:description:description\">&nbsp;<\/div>\n<h3><span style=\"vertical-align: inherit\">Course details: IP Verification using System Verilog (SV) with Project Demo<\/span><\/h3>\n<ul>\n<li>Publisher : <a href=\"https:\/\/href.li\/?https:\/\/www.udemy.com\/course\/ip-verification-using-system-verilog-part-i\/?couponCode=LEARNNOWPLANSGB\" target=\"_blank\" rel=\"noopener\">Udemy<\/a><\/li>\n<li>Teacher : <a href=\"https:\/\/downloadlynet.ir\/tag\/vlsi-mentor\">VLSI Mentor<\/a><\/li>\n<li>Language: English<\/li>\n<li>Level : Expert<\/li>\n<li>Lectures : 12<\/li>\n<li>Duration : 18 hours and 40 minutes<\/li>\n<\/ul>\n<h3><span style=\"vertical-align: inherit\">Course syllabus<\/span><\/h3>\n<h2>&nbsp;<img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-full wp-image-1004323\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2025\/09\/ASIC-Verification-using-System-Verilog-SV-Project-Demo.c.jpeg\" alt=\"ASIC Verification using System Verilog (SV) + Project Demo\" width=\"705\" height=\"196\"><\/h2>\n<h3><span style=\"vertical-align: inherit\">Course prerequisites<\/span><\/h3>\n<div class=\"ud-block-list-item ud-block-list-item-small ud-block-list-item-tight ud-block-list-item-neutral ud-text-sm\">\n<ul>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Digital fundamentals<\/span><\/li>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Verilog language<\/span><\/li>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Basics of Verification<\/span><\/li>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Linux commands<\/span><\/li>\n<\/ul>\n<\/div>\n<h3><span style=\"vertical-align: inherit\">Course images<\/span><\/h3>\n<h2><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-full wp-image-1004324\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2025\/09\/ASIC-Verification-using-System-Verilog-SV-Project-Demo.d.jpeg\" alt=\"ASIC Verification using System Verilog (SV) + Project Demo\" width=\"705\" height=\"243\"><\/h2>\n<h3><span style=\"vertical-align: inherit\">Sample course video<\/span><\/h3>\n<div style=\"width: 640px;\" class=\"wp-video\"><span class=\"mejs-offscreen\">Video Player<\/span><\/p>\n<div id=\"mep_0\" class=\"mejs-container mejs-container-keyboard-inactive wp-video-shortcode mejs-video\" tabindex=\"0\" role=\"application\" aria-label=\"Video Player\" style=\"width: 640px; height: 360px; min-width: 217px;\">\n<div class=\"mejs-inner\">\n<div class=\"mejs-mediaelement\"><mediaelementwrapper id=\"video-156593-1\"><video class=\"wp-video-shortcode\" id=\"video-156593-1_html5\" width=\"640\" height=\"360\" preload=\"metadata\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/IP_Verification_using_System_Verilog_SV_with_Project_Demo_Downloadly.ir.mp4?_=1\" style=\"width: 640px; height: 360px;\"><source type=\"video\/mp4\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/IP_Verification_using_System_Verilog_SV_with_Project_Demo_Downloadly.ir.mp4?_=1\"><a href=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/IP_Verification_using_System_Verilog_SV_with_Project_Demo_Downloadly.ir.mp4?nocache=1786113459136\">https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/IP_Verification_using_System_Verilog_SV_with_Project_Demo_Downloadly.ir.mp4<\/a><\/video><\/mediaelementwrapper><\/div>\n<div class=\"mejs-layers\">\n<div class=\"mejs-poster mejs-layer\" style=\"display: none; width: 100%; height: 100%;\"><\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-loading\"><span class=\"mejs-overlay-loading-bg-img\"><\/span><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-error\"><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer mejs-overlay-play\" style=\"width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-button\" role=\"button\" tabindex=\"0\" aria-label=\"Play\" aria-pressed=\"false\"><\/div>\n<\/div>\n<\/div>\n<div class=\"mejs-controls\">\n<div class=\"mejs-button mejs-playpause-button mejs-play\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Play\" aria-label=\"Play\" tabindex=\"0\"><\/button><\/div>\n<div class=\"mejs-time mejs-currenttime-container\" role=\"timer\" aria-live=\"off\"><span class=\"mejs-currenttime\">00:00<\/span><\/div>\n<div class=\"mejs-time-rail\"><span class=\"mejs-time-total mejs-time-slider\" role=\"slider\" tabindex=\"0\" aria-label=\"Time Slider\" aria-valuemin=\"0\" aria-valuemax=\"0\" aria-valuenow=\"0\" aria-valuetext=\"00:00\"><span class=\"mejs-time-buffering\" style=\"display: none;\"><\/span><span class=\"mejs-time-loaded\"><\/span><span class=\"mejs-time-current\"><\/span><span class=\"mejs-time-hovered no-hover\"><\/span><span class=\"mejs-time-handle\"><span class=\"mejs-time-handle-content\"><\/span><\/span><span class=\"mejs-time-float\"><span class=\"mejs-time-float-current\">00:00<\/span><span class=\"mejs-time-float-corner\"><\/span><\/span><\/span><\/div>\n<div class=\"mejs-time mejs-duration-container\"><span class=\"mejs-duration\">00:00<\/span><\/div>\n<div class=\"mejs-button mejs-volume-button mejs-mute\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Mute\" aria-label=\"Mute\" tabindex=\"0\"><\/button><a href=\"javascript:void(0);\" class=\"mejs-volume-slider\" aria-label=\"Volume Slider\" aria-valuemin=\"0\" aria-valuemax=\"100\" role=\"slider\" aria-orientation=\"vertical\"><span class=\"mejs-offscreen\">Use Up\/Down Arrow keys to increase or decrease volume.<\/span><\/p>\n<div class=\"mejs-volume-total\">\n<div class=\"mejs-volume-current\" style=\"bottom: 0px; height: 100%;\"><\/div>\n<div class=\"mejs-volume-handle\" style=\"bottom: 100%; margin-bottom: -3px;\"><\/div>\n<\/div>\n<p><\/a><\/div>\n<div class=\"mejs-button mejs-fullscreen-button\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Fullscreen\" aria-label=\"Fullscreen\" tabindex=\"0\"><\/button><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div>\n<h3><span style=\"vertical-align: inherit\">Installation Guide<\/span><\/h3>\n<p><span style=\"vertical-align: inherit\">After Extract, view with your favorite player.<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Subtitles: English<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Quality: 1080p<\/span><\/p>\n<\/div>\n<p>The 2025\/7 version has the duration decreased by 1 minutes compared to 2024\/11.<\/p>\n<h3><span style=\"vertical-align: inherit\">Download link<\/span><\/h3>\n<p><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_ASIC_Verification_using_System_Verilog_SV_Project_Demo_1080_2025-7_Downloadly.ir.part1.rar?nocache=1786113453\">DownloadPart 1 \u2013 2 GB<\/a><\/p>\n<p><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_ASIC_Verification_using_System_Verilog_SV_Project_Demo_1080_2025-7_Downloadly.ir.part2.rar?nocache=1786113453\">DownloadPart 2 \u2013 2 GB<\/a><\/p>\n<p><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_ASIC_Verification_using_System_Verilog_SV_Project_Demo_1080_2025-7_Downloadly.ir.part3.rar?nocache=1786113453\">DownloadPart 3 \u2013 2 GB<\/a><\/p>\n<p><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_ASIC_Verification_using_System_Verilog_SV_Project_Demo_1080_2025-7_Downloadly.ir.part4.rar?nocache=1786113453\">DownloadPart 4 \u2013 2 GB<\/a><\/p>\n<p><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_ASIC_Verification_using_System_Verilog_SV_Project_Demo_1080_2025-7_Downloadly.ir.part5.rar?nocache=1786113453\">DownloadPart 5 \u2013 2 GB<\/a><\/p>\n<p><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_ASIC_Verification_using_System_Verilog_SV_Project_Demo_1080_2025-7_Downloadly.ir.part6.rar?nocache=1786113453\">DownloadPart 6 \u2013 1.93 GB<\/a><\/p>\n<p><span style=\"vertical-align: inherit\">File(s) password: www.downloadly.ir<\/span><\/p>\n<h3><span style=\"vertical-align: inherit\">File size<\/span><\/h3>\n<p>11.93 GB<\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp; Description IP Verification using System Verilog (SV) with Project Demo course. This course is designed for beginners to experts. The content of this Sys<\/p>\n","protected":false},"author":1,"template":"","dgi_category":[10458],"dgi_tag":[77545,77546,77547,77548,77549,77550],"class_list":["post-8861","digital_item","type-digital_item","status-publish","has-post-thumbnail","hentry","dgi_category-video-tutorials","dgi_tag-course-ip-verification-using-system-verilog-sv-with-project-demo","dgi_tag-download-course-ip-verification-using-system-verilog-sv-with-project-demo","dgi_tag-download-ip-verification-using-system-verilog-sv-with-project-demo","dgi_tag-free-download-ip-verification-using-system-verilog-sv-with-project-demo","dgi_tag-free-ip-verification-using-system-verilog-sv-with-project-demo","dgi_tag-vlsi-mentor"],"_links":{"self":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/8861","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item"}],"about":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/types\/digital_item"}],"author":[{"embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"version-history":[{"count":0,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/8861\/revisions"}],"wp:attachment":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/media?parent=8861"}],"wp:term":[{"taxonomy":"dgi_category","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_category?post=8861"},{"taxonomy":"dgi_tag","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_tag?post=8861"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}