{"id":6532,"date":"2026-08-10T09:34:26","date_gmt":"2026-08-10T09:34:26","guid":{"rendered":"https:\/\/nokobox.com\/index.php\/item\/udemy-systemverilog-uvm-for-asic-soc-verification-part-1-2024-8\/"},"modified":"2026-08-10T09:34:26","modified_gmt":"2026-08-10T09:34:26","slug":"udemy-systemverilog-uvm-for-asic-soc-verification-part-1-2024-8","status":"publish","type":"digital_item","link":"https:\/\/nokobox.com\/index.php\/item\/udemy-systemverilog-uvm-for-asic-soc-verification-part-1-2024-8\/","title":{"rendered":"Udemy \u2013 SystemVerilog\/UVM for ASIC\/SoC Verification Part 1 2024-8"},"content":{"rendered":"<div class=\"w-post-elm post_content\">\n<h2 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Description<\/span><\/h2>\n<p dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"5:1-5:91\"><span style=\"vertical-align: inherit\">SystemVerilog\/UVM for ASIC\/SoC Verification Course Part 1. Are you ready to enter the world of SystemVerilog and unlock its potential for industrial-scale design and verification? Designed specifically by the Quant Semicon team, our comprehensive course is for beginners and advanced learners who want to master SystemVerilog (SV) and its Object Oriented Programming (OOP) concepts. With a hands-on approach and real-world examples, this course takes you from SV basics to advanced applications, preparing you for the challenges of the semiconductor industry. By the end of this course, you will have a strong foundation in VLSI verification principles and hands-on experience, and be ready to tackle complex verification challenges in industry. Whether you\u2019re a student preparing for a career in the semiconductor industry or a professional looking to sharpen your skills, this course provides a complete, structured path to mastering SystemVerilog. Join us and take the first step to becoming a SystemVerilog expert!<\/span><\/p>\n<h3 dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"11:1-11:86\"><span style=\"vertical-align: inherit\">What you will learn in the SystemVerilog\/UVM for ASIC\/SoC Verification Part 1 course<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"13:1-19:0\">\n<li data-sourcepos=\"13:1-13:94\"><span style=\"vertical-align: inherit\">Learn the basics of SystemVerilog, different data types, procedural blocks and control flow structures.<\/span><\/li>\n<li data-sourcepos=\"14:1-14:78\"><span style=\"vertical-align: inherit\">Explore how to facilitate reusable and scalable testbenches with OOP concepts.<\/span><\/li>\n<li data-sourcepos=\"15:1-15:90\"><span style=\"vertical-align: inherit\">Learn how to use SystemVerilog interfaces to simplify the connection between design modules.<\/span><\/li>\n<li data-sourcepos=\"16:1-16:78\"><span style=\"vertical-align: inherit\">Learn how to verify correct master-slave interaction and signal behavior in APB transactions.<\/span><\/li>\n<li data-sourcepos=\"17:1-17:19\"><span style=\"vertical-align: inherit\">Learn the basics of UVM<\/span><\/li>\n<li data-sourcepos=\"18:1-19:0\"><span style=\"vertical-align: inherit\">On-chip design verification concepts<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"20:1-20:30\"><span style=\"vertical-align: inherit\">This course is suitable for people who<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"22:1-24:0\">\n<li data-sourcepos=\"22:1-22:56\"><span style=\"vertical-align: inherit\">Students: Electronics, Microelectronics, VLSI, Embedded<\/span><\/li>\n<li data-sourcepos=\"23:1-24:0\"><span style=\"vertical-align: inherit\">Employed professionals: VLSI design specialist, verification engineers, verification supervisors<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Course specifications SystemVerilog\/UVM for ASIC\/SoC Verification Part 1<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\">\n<li><span style=\"vertical-align: inherit\">Publisher:&nbsp; <\/span><a href=\"https:\/\/href.li\/?https:\/\/www.udemy.com\/course\/systemveriloguvm-for-asicsoc-verification-part-1\/\" target=\"_blank\" rel=\"noopener\"><span style=\"vertical-align: inherit\">Udemy<\/span><\/a><\/li>\n<li><span style=\"vertical-align: inherit\">Lecturer:&nbsp; <\/span><a class=\"ud-btn ud-btn-large ud-btn-link ud-heading-md ud-text-sm ud-instructor-links\" href=\"https:\/\/downloadlynet.ir\/tag\/quant-semicon\/\" data-position=\"1\"><span class=\"ud-btn-label\"><span style=\"vertical-align: inherit\">Quant Semicon<\/span><\/span><\/a><\/li>\n<li><span style=\"vertical-align: inherit\">Training level: beginner to advanced<\/span><\/li>\n<li><span style=\"vertical-align: inherit\">Training duration: 4 hours and 45 minutes<\/span><\/li>\n<li><span style=\"vertical-align: inherit\">Number of courses: 14<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Headlines of the course on 2024\/9<\/span><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-938701 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2024\/10\/SystemVerilog-UVM-for-ASIC-SoC-Verification-Part-1-1.jpg\" alt=\"SystemVerilog\/UVM for ASIC\/SoC Verification Part 1\" width=\"884\" height=\"127\"><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">SystemVerilog\/UVM for ASIC\/SoC Verification Part 1 course prerequisites<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\">\n<li dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Digital Design<\/span><\/li>\n<li dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Logic design flow<\/span><\/li>\n<li dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Verilog<\/span><\/li>\n<li dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Digital Electronics<\/span><\/li>\n<li dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Basic programming knowledge<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Course images<\/span><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-938702 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2024\/10\/SystemVerilog-UVM-for-ASIC-SoC-Verification-Part-1.jpg\" alt=\"SystemVerilog\/UVM for ASIC\/SoC Verification Part 1\" width=\"776\" height=\"389\"><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Sample video of the course<\/span><\/h3>\n<div style=\"width: 640px;\" class=\"wp-video\"><span class=\"mejs-offscreen\">Video Player<\/span><\/p>\n<div id=\"mep_0\" class=\"mejs-container mejs-container-keyboard-inactive wp-video-shortcode mejs-video\" tabindex=\"0\" role=\"application\" aria-label=\"Video Player\" style=\"width: 640px; height: 360px; min-width: 217px;\">\n<div class=\"mejs-inner\">\n<div class=\"mejs-mediaelement\"><mediaelementwrapper id=\"video-143780-1\"><video class=\"wp-video-shortcode\" id=\"video-143780-1_html5\" width=\"640\" height=\"360\" preload=\"metadata\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/SystemVerilogUVM_for_ASICSoC_Verification_Part1_Downloadly.ir.mp4?_=1\" style=\"width: 640px; height: 360px;\"><source type=\"video\/mp4\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/SystemVerilogUVM_for_ASICSoC_Verification_Part1_Downloadly.ir.mp4?_=1\"><a href=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/SystemVerilogUVM_for_ASICSoC_Verification_Part1_Downloadly.ir.mp4?nocache=1786107472438\">https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/SystemVerilogUVM_for_ASICSoC_Verification_Part1_Downloadly.ir.mp4<\/a><\/video><\/mediaelementwrapper><\/div>\n<div class=\"mejs-layers\">\n<div class=\"mejs-poster mejs-layer\" style=\"display: none; width: 100%; height: 100%;\"><\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-loading\"><span class=\"mejs-overlay-loading-bg-img\"><\/span><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-error\"><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer mejs-overlay-play\" style=\"width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-button\" role=\"button\" tabindex=\"0\" aria-label=\"Play\" aria-pressed=\"false\"><\/div>\n<\/div>\n<\/div>\n<div class=\"mejs-controls\">\n<div class=\"mejs-button mejs-playpause-button mejs-play\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Play\" aria-label=\"Play\" tabindex=\"0\"><\/button><\/div>\n<div class=\"mejs-time mejs-currenttime-container\" role=\"timer\" aria-live=\"off\"><span class=\"mejs-currenttime\">00:00<\/span><\/div>\n<div class=\"mejs-time-rail\"><span class=\"mejs-time-total mejs-time-slider\" role=\"slider\" tabindex=\"0\" aria-label=\"Time Slider\" aria-valuemin=\"0\" aria-valuemax=\"0\" aria-valuenow=\"0\" aria-valuetext=\"00:00\"><span class=\"mejs-time-buffering\" style=\"display: none;\"><\/span><span class=\"mejs-time-loaded\"><\/span><span class=\"mejs-time-current\"><\/span><span class=\"mejs-time-hovered no-hover\"><\/span><span class=\"mejs-time-handle\"><span class=\"mejs-time-handle-content\"><\/span><\/span><span class=\"mejs-time-float\"><span class=\"mejs-time-float-current\">00:00<\/span><span class=\"mejs-time-float-corner\"><\/span><\/span><\/span><\/div>\n<div class=\"mejs-time mejs-duration-container\"><span class=\"mejs-duration\">00:00<\/span><\/div>\n<div class=\"mejs-button mejs-volume-button mejs-mute\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Mute\" aria-label=\"Mute\" tabindex=\"0\"><\/button><a href=\"javascript:void(0);\" class=\"mejs-volume-slider\" aria-label=\"Volume Slider\" aria-valuemin=\"0\" aria-valuemax=\"100\" role=\"slider\" aria-orientation=\"vertical\"><span class=\"mejs-offscreen\">Use Up\/Down Arrow keys to increase or decrease volume.<\/span><\/p>\n<div class=\"mejs-volume-total\">\n<div class=\"mejs-volume-current\" style=\"bottom: 0px; height: 100%;\"><\/div>\n<div class=\"mejs-volume-handle\" style=\"bottom: 100%; margin-bottom: -3px;\"><\/div>\n<\/div>\n<p><\/a><\/div>\n<div class=\"mejs-button mejs-fullscreen-button\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Fullscreen\" aria-label=\"Fullscreen\" tabindex=\"0\"><\/button><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div dir=\"ltr\" style=\"text-align: left\">\n<h3><span style=\"vertical-align: inherit\">Installation guide<\/span><\/h3>\n<p><span style=\"vertical-align: inherit\">After Extract, view with your favorite Player.<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Subtitle: None<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Quality: 1080p<\/span><\/p>\n<\/div>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">download link<\/span><\/h3>\n<p dir=\"ltr\" style=\"text-align: left\"><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_SystemVerilogUVM_for_ASICSoC_Verification_Part1_2024-8.part1_Downloadly.ir.rar?nocache=1786107471\"><span style=\"vertical-align: inherit\">Download part 1 \u2013 1 GB<\/span><\/a><\/p>\n<p dir=\"ltr\" style=\"text-align: left\"><a href=\"https:\/\/dl2.downloadly.ir\/Files\/Elearning\/Udemy_SystemVerilogUVM_for_ASICSoC_Verification_Part1_2024-8.part2_Downloadly.ir.rar?nocache=1786107471\"><span style=\"vertical-align: inherit\">Download part 2 \u2013 59 MB<\/span><\/a><\/p>\n<p dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">File(s) password: www.downloadly.ir<\/span><\/p>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">File size<\/span><\/h3>\n<p dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">1.05 GB<\/span><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Description SystemVerilog\/UVM for ASIC\/SoC Verification Course Part 1. Are you ready to enter the world of SystemVerilog and unlock its potential for industrial<\/p>\n","protected":false},"author":1,"template":"","dgi_category":[10458],"dgi_tag":[61779,61780,61781,61782,61783,61784],"class_list":["post-6532","digital_item","type-digital_item","status-publish","has-post-thumbnail","hentry","dgi_category-video-tutorials","dgi_tag-course-systemverilog-uvm-for-asic-soc-verification-part-1","dgi_tag-download-course-systemverilog-uvm-for-asic-soc-verification-part-1","dgi_tag-download-systemverilog-uvm-for-asic-soc-verification-part-1","dgi_tag-free-download-systemverilog-uvm-for-asic-soc-verification-part-1","dgi_tag-free-systemverilog-uvm-for-asic-soc-verification-part-1","dgi_tag-quant-semicon"],"_links":{"self":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/6532","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item"}],"about":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/types\/digital_item"}],"author":[{"embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"version-history":[{"count":0,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/6532\/revisions"}],"wp:attachment":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/media?parent=6532"}],"wp:term":[{"taxonomy":"dgi_category","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_category?post=6532"},{"taxonomy":"dgi_tag","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_tag?post=6532"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}