{"id":3933,"date":"2026-08-10T09:08:51","date_gmt":"2026-08-10T09:08:51","guid":{"rendered":"https:\/\/nokobox.com\/index.php\/item\/udemy-hands-on-fpga-project-design-from-scratch-using-verilog-2024-5\/"},"modified":"2026-08-10T09:08:51","modified_gmt":"2026-08-10T09:08:51","slug":"udemy-hands-on-fpga-project-design-from-scratch-using-verilog-2024-5","status":"publish","type":"digital_item","link":"https:\/\/nokobox.com\/index.php\/item\/udemy-hands-on-fpga-project-design-from-scratch-using-verilog-2024-5\/","title":{"rendered":"Udemy \u2013 hands-on fpga project design from scratch using verilog 2024-5"},"content":{"rendered":"<div class=\"w-post-elm post_content\">\n<h2 dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"3:1-3:16\"><span style=\"vertical-align: inherit\">Description<\/span><\/h2>\n<p dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"5:1-5:201\"><span style=\"vertical-align: inherit\">hands-on fpga project design course from scratch using verilog. In this course, you will learn how to design a real project on FPGA using System Verilog. I will introduce you to free software used for analysis, synthesis, RTL simulation and verification. We start by learning how to translate design specifications that allow you to select input and output ports. Then you will learn how to separate the design into modules and further separate modules into sub-modules. At the end of the course, you will receive a practical task that will further strengthen your knowledge of designing FPGA projects. We also test the final design and see how they work in the real world. Simulation is done in both Logism and Quartus.<\/span><\/p>\n<h3 dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"15:1-15:29\"><span style=\"vertical-align: inherit\">What you will learn in the course<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"17:1-21:0\">\n<li data-sourcepos=\"17:1-17:91\"><span style=\"vertical-align: inherit\">Apply your knowledge of Verilog to design a real practical project using Verilog.<\/span><\/li>\n<li data-sourcepos=\"18:1-18:118\"><span style=\"vertical-align: inherit\">Learn how to translate design specifications for a real FPGA Verilog project, for example how to assign I\/O ports.<\/span><\/li>\n<li data-sourcepos=\"19:1-19:86\"><span style=\"vertical-align: inherit\">Learn how to break down complex designs into modules and sub-modules before the initial design.<\/span><\/li>\n<li data-sourcepos=\"20:1-21:0\"><span style=\"vertical-align: inherit\">Learn the basic steps required for any FPGA development, including allocation, design, configuration of modules, and separation of sub-modules.<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"22:1-22:37\"><span style=\"vertical-align: inherit\">Who is this course suitable for?<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\" data-sourcepos=\"24:1-26:0\">\n<li data-sourcepos=\"24:1-24:49\"><span style=\"vertical-align: inherit\">Verilog, FPGA hardware developers and engineers<\/span><\/li>\n<li data-sourcepos=\"25:1-26:0\"><span style=\"vertical-align: inherit\">Interested in learning FPGA design using Verilog<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Specifications of hands-on fpga project design from scratch using verilog course<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\">\n<li><span style=\"vertical-align: inherit\">Publisher:&nbsp; <\/span><a href=\"https:\/\/href.li\/?https:\/\/www.udemy.com\/course\/hands-on-fpga-project-design-from-scratch-using-verilog\/?couponCode=OF53124\" target=\"_blank\"><span style=\"vertical-align: inherit\">Udemy<\/span><\/a><\/li>\n<li><span style=\"vertical-align: inherit\">Lecturer:&nbsp; <\/span><a class=\"ud-btn ud-btn-large ud-btn-link ud-heading-md ud-text-sm ud-instructor-links\" href=\"https:\/\/downloadlynet.ir\/tag\/ezeuko-emmanuel\/\" data-position=\"1\"><span style=\"vertical-align: inherit\">Ezeuko Emmanuel<\/span><\/a><\/li>\n<li><span style=\"vertical-align: inherit\">Training level: beginner to advanced<\/span><\/li>\n<li><span style=\"vertical-align: inherit\">Training duration: 4 hours and 9 minutes<\/span><\/li>\n<li><span style=\"vertical-align: inherit\">Number of courses: 13<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Course headings<\/span><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-908668 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2024\/06\/hands-on-fpga-project-design-from-scratch-using-verilog-1.jpg\" alt=\"hands-on fpga project design from scratch using verilog\" width=\"882\" height=\"114\"><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Course prerequisites<\/span><\/h3>\n<div class=\"ud-block-list-item ud-block-list-item-small ud-block-list-item-tight ud-block-list-item-neutral ud-text-sm\" dir=\"ltr\" style=\"text-align: left\">\n<ul>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">basic syntax of verilog, system verilog or VHDL but not compulsory<\/span><\/li>\n<\/ul>\n<\/div>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Course images<\/span><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-908669 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2024\/06\/hands-on-fpga-project-design-from-scratch-using-verilog.jpg\" alt=\"hands-on fpga project design from scratch using verilog\" width=\"836\" height=\"316\"><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Sample video of the course<\/span><\/h3>\n<div style=\"width: 640px;\" class=\"wp-video\"><span class=\"mejs-offscreen\">Video Player<\/span><\/p>\n<div id=\"mep_0\" class=\"mejs-container mejs-container-keyboard-inactive wp-video-shortcode mejs-video\" tabindex=\"0\" role=\"application\" aria-label=\"Video Player\" style=\"width: 640px; height: 360px; min-width: 217px;\">\n<div class=\"mejs-inner\">\n<div class=\"mejs-mediaelement\"><mediaelementwrapper id=\"video-129520-1\"><video class=\"wp-video-shortcode\" id=\"video-129520-1_html5\" width=\"640\" height=\"360\" preload=\"metadata\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/hands-on_fpga_project_design_from_scratch_using_verilog_Downloadly.ir.mp4?_=1\" style=\"width: 640px; height: 360px;\"><source type=\"video\/mp4\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/hands-on_fpga_project_design_from_scratch_using_verilog_Downloadly.ir.mp4?_=1\"><a href=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/hands-on_fpga_project_design_from_scratch_using_verilog_Downloadly.ir.mp4?nocache=1786099859278\">https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/hands-on_fpga_project_design_from_scratch_using_verilog_Downloadly.ir.mp4<\/a><\/video><\/mediaelementwrapper><\/div>\n<div class=\"mejs-layers\">\n<div class=\"mejs-poster mejs-layer\" style=\"display: none; width: 100%; height: 100%;\"><\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-loading\"><span class=\"mejs-overlay-loading-bg-img\"><\/span><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-error\"><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer mejs-overlay-play\" style=\"width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-button\" role=\"button\" tabindex=\"0\" aria-label=\"Play\" aria-pressed=\"false\"><\/div>\n<\/div>\n<\/div>\n<div class=\"mejs-controls\">\n<div class=\"mejs-button mejs-playpause-button mejs-play\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Play\" aria-label=\"Play\" tabindex=\"0\"><\/button><\/div>\n<div class=\"mejs-time mejs-currenttime-container\" role=\"timer\" aria-live=\"off\"><span class=\"mejs-currenttime\">00:00<\/span><\/div>\n<div class=\"mejs-time-rail\"><span class=\"mejs-time-total mejs-time-slider\" role=\"slider\" tabindex=\"0\" aria-label=\"Time Slider\" aria-valuemin=\"0\" aria-valuemax=\"0\" aria-valuenow=\"0\" aria-valuetext=\"00:00\"><span class=\"mejs-time-buffering\" style=\"display: none;\"><\/span><span class=\"mejs-time-loaded\"><\/span><span class=\"mejs-time-current\"><\/span><span class=\"mejs-time-hovered no-hover\"><\/span><span class=\"mejs-time-handle\"><span class=\"mejs-time-handle-content\"><\/span><\/span><span class=\"mejs-time-float\"><span class=\"mejs-time-float-current\">00:00<\/span><span class=\"mejs-time-float-corner\"><\/span><\/span><\/span><\/div>\n<div class=\"mejs-time mejs-duration-container\"><span class=\"mejs-duration\">00:00<\/span><\/div>\n<div class=\"mejs-button mejs-volume-button mejs-mute\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Mute\" aria-label=\"Mute\" tabindex=\"0\"><\/button><a href=\"javascript:void(0);\" class=\"mejs-volume-slider\" aria-label=\"Volume Slider\" aria-valuemin=\"0\" aria-valuemax=\"100\" role=\"slider\" aria-orientation=\"vertical\"><span class=\"mejs-offscreen\">Use Up\/Down Arrow keys to increase or decrease volume.<\/span><\/p>\n<div class=\"mejs-volume-total\">\n<div class=\"mejs-volume-current\" style=\"bottom: 0px; height: 100%;\"><\/div>\n<div class=\"mejs-volume-handle\" style=\"bottom: 100%; margin-bottom: -3px;\"><\/div>\n<\/div>\n<p><\/a><\/div>\n<div class=\"mejs-button mejs-fullscreen-button\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Fullscreen\" aria-label=\"Fullscreen\" tabindex=\"0\"><\/button><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div dir=\"ltr\" style=\"text-align: left\">\n<h3><span style=\"vertical-align: inherit\">Installation guide<\/span><\/h3>\n<p><span style=\"vertical-align: inherit\">After Extract, view with your favorite Player.<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Subtitle: None<\/span><\/p>\n<p><span style=\"vertical-align: inherit\">Quality: 720p<\/span><\/p>\n<\/div>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">download link<\/span><\/h3>\n<p dir=\"ltr\" style=\"text-align: left\"><a href=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Udemy_hands-on_fpga_project_design_from_scratch_using_verilog_2024-5.part1_Downloadly.ir.rar?nocache=1786099858\"><span style=\"vertical-align: inherit\">Download part 1 \u2013 1 GB<\/span><\/a><\/p>\n<p dir=\"ltr\" style=\"text-align: left\"><a href=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Udemy_hands-on_fpga_project_design_from_scratch_using_verilog_2024-5.part2_Downloadly.ir.rar?nocache=1786099858\"><span style=\"vertical-align: inherit\">Download part 2 \u2013 835 MB<\/span><\/a><\/p>\n<p dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">File(s) password: www.downloadly.ir<\/span><\/p>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">Size<\/span><\/h3>\n<p dir=\"ltr\" style=\"text-align: left\"><span style=\"vertical-align: inherit\">1.8 GB<\/span><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Description hands-on fpga project design course from scratch using verilog. In this course, you will learn how to design a real project on FPGA using System Ver<\/p>\n","protected":false},"author":1,"template":"","dgi_category":[10458],"dgi_tag":[43537,43538,43539,43540,43541,43542],"class_list":["post-3933","digital_item","type-digital_item","status-publish","has-post-thumbnail","hentry","dgi_category-video-tutorials","dgi_tag-course-hands-on-fpga-project-design-from-scratch-using-verilog","dgi_tag-download-course-hands-on-fpga-project-design-from-scratch-using-verilog","dgi_tag-download-hands-on-fpga-project-design-from-scratch-using-verilog","dgi_tag-ezeuko-emmanuel","dgi_tag-free-download-hands-on-fpga-project-design-from-scratch-using-verilog","dgi_tag-free-hands-on-fpga-project-design-from-scratch-using-verilog"],"_links":{"self":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/3933","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item"}],"about":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/types\/digital_item"}],"author":[{"embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"version-history":[{"count":0,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/3933\/revisions"}],"wp:attachment":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/media?parent=3933"}],"wp:term":[{"taxonomy":"dgi_category","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_category?post=3933"},{"taxonomy":"dgi_tag","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_tag?post=3933"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}