{"id":13598,"date":"2026-08-10T11:01:34","date_gmt":"2026-08-10T11:01:34","guid":{"rendered":"https:\/\/nokobox.com\/index.php\/item\/udemy-fpga101-digital-system-design-using-verilog-and-python-2025-9\/"},"modified":"2026-08-10T11:01:34","modified_gmt":"2026-08-10T11:01:34","slug":"udemy-fpga101-digital-system-design-using-verilog-and-python-2025-9","status":"publish","type":"digital_item","link":"https:\/\/nokobox.com\/index.php\/item\/udemy-fpga101-digital-system-design-using-verilog-and-python-2025-9\/","title":{"rendered":"Udemy \u2013 FPGA101: Digital System Design using Verilog and Python 2025-9"},"content":{"rendered":"<div class=\"w-post-elm post_content\">\n<h2 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Description<\/span><\/h2>\n<p dir=\"ltr\" style=\"text-align: left\" data-path-to-node=\"8\"><span dir=\"auto\" style=\"vertical-align: inherit\">FPGA101: Digital System Design using Verilog and Python. This course teaches the fundamentals of digital system design using Verilog, implementing circuits on an FPGA, and interfacing with an ARM processor. FPGAs are commonly used for computational acceleration in digital signal processing, as well as for verifying circuits before final fabrication as application-specific integrated circuits (ASICs). Focusing on the Verilog language, this course covers the fundamentals of digital circuit design, including combinational logic, sequential logic, finite state machines, and finite state machines with data paths. It also provides three additional topics on integrating digital circuitry on an FPGA with an ARM processor. At the end of the course, a final project is conducted on how to build a tensor processing unit similar to the Google TPU. In this project, participants learn the methodology for designing an accelerator for a neural network based on matrix multiplication. This methodology can be extended to other designs of interest and has wide application in engineering.<\/span><\/p>\n<h3 dir=\"ltr\" style=\"text-align: left\" data-path-to-node=\"11\"><span dir=\"auto\" style=\"vertical-align: inherit\">What you will learn<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\">\n<li data-path-to-node=\"12,0,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Verilog and FPGA Basics:<\/span><\/li>\n<li data-path-to-node=\"12,0,1,0,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Understand the principles of Verilog and FPGA.<\/span><\/li>\n<li data-path-to-node=\"12,1,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">RTL design:<\/span><\/li>\n<li data-path-to-node=\"12,1,1,0,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Understanding of RTL design, including combinational logic, sequential logic, FSM and FSMD.<\/span><\/li>\n<li data-path-to-node=\"12,2,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Interface with ARM processor:<\/span><\/li>\n<li data-path-to-node=\"12,2,1,0,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Connecting digital circuitry on an FPGA to an ARM processor.<\/span><\/li>\n<li data-path-to-node=\"12,3,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">TPU construction:<\/span><\/li>\n<li data-path-to-node=\"12,3,1,0,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Building a small TPU like Google\u2019s TPU.<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\" data-path-to-node=\"14\"><span dir=\"auto\" style=\"vertical-align: inherit\">This course is suitable for people who:<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\" data-path-to-node=\"15\">\n<li>\n<p data-path-to-node=\"15,0,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Anyone interested in learning the fundamentals of digital system design.<\/span><\/p>\n<\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\" data-path-to-node=\"17\"><span dir=\"auto\" style=\"vertical-align: inherit\">Course details<\/span><\/h3>\n<ul dir=\"ltr\" style=\"text-align: left\">\n<li data-path-to-node=\"18,0,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Publisher: <\/span><a href=\"https:\/\/href.li\/?https:\/\/www.udemy.com\/course\/fpga101-digital-system-design-using-verilog-and-python\/?couponCode=KEEPLEARNING\" target=\"_blank\" rel=\"noopener\"><span dir=\"auto\" style=\"vertical-align: inherit\">Udemy<\/span><\/a><\/li>\n<li data-path-to-node=\"18,1,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Instructor: <\/span><a href=\"https:\/\/downloadlynet.ir\/tag\/erwin-ouyang\/\"><span dir=\"auto\" style=\"vertical-align: inherit\">Erwin Ouyang<\/span><\/a><\/li>\n<li data-path-to-node=\"18,2,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Training level: Beginner to advanced<\/span><\/li>\n<li data-path-to-node=\"18,3,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Training duration: 2 hours and 49 minutes<\/span><\/li>\n<li data-path-to-node=\"18,4,0\"><span dir=\"auto\" style=\"vertical-align: inherit\">Number of lessons: 25<\/span><\/li>\n<\/ul>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Course headings<\/span><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-1023576 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2025\/12\/FPGA101-Digital-System-Design-using-Verilog-and-Python-1.png\" alt=\"FPGA101: Digital System Design using Verilog and Python\" width=\"886\" height=\"607\"><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Prerequisites for FPGA101: Digital System Design using Verilog and Python<\/span><\/h3>\n<div class=\"ud-block-list-item ud-block-list-item-small ud-block-list-item-tight ud-block-list-item-neutral ud-text-sm\" dir=\"ltr\" style=\"text-align: left\">\n<ul>\n<li class=\"ud-block-list-item-content\" dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Fundamentals of digital circuits and programming will give an added advantage.<\/span><\/li>\n<\/ul>\n<\/div>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Course images<\/span><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-1023577 size-full\" src=\"https:\/\/downloadly.ir\/wp-content\/uploads\/2025\/12\/FPGA101-Digital-System-Design-using-Verilog-and-Python.png\" alt=\"FPGA101: Digital System Design using Verilog and Python\" width=\"862\" height=\"380\"><\/h3>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Sample course video<\/span><\/h3>\n<div style=\"width: 640px;\" class=\"wp-video\"><span class=\"mejs-offscreen\">Video Player<\/span><\/p>\n<div id=\"mep_0\" class=\"mejs-container mejs-container-keyboard-inactive wp-video-shortcode mejs-video\" tabindex=\"0\" role=\"application\" aria-label=\"Video Player\" style=\"width: 640px; height: 360px; min-width: 217px;\">\n<div class=\"mejs-inner\">\n<div class=\"mejs-mediaelement\"><mediaelementwrapper id=\"video-186861-1\"><video class=\"wp-video-shortcode\" id=\"video-186861-1_html5\" width=\"640\" height=\"360\" preload=\"metadata\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/FPGA101_Digital_System_Design_using_Verilog_and_Python_Downloadly.ir.mp4?_=1\" style=\"width: 640px; height: 360px;\"><source type=\"video\/mp4\" src=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/FPGA101_Digital_System_Design_using_Verilog_and_Python_Downloadly.ir.mp4?_=1\"><a href=\"https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/FPGA101_Digital_System_Design_using_Verilog_and_Python_Downloadly.ir.mp4?nocache=1786176043611\">https:\/\/dl.downloadly.ir\/Files\/Elearning\/Sample\/FPGA101_Digital_System_Design_using_Verilog_and_Python_Downloadly.ir.mp4<\/a><\/video><\/mediaelementwrapper><\/div>\n<div class=\"mejs-layers\">\n<div class=\"mejs-poster mejs-layer\" style=\"display: none; width: 100%; height: 100%;\"><\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-loading\"><span class=\"mejs-overlay-loading-bg-img\"><\/span><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer\" style=\"display: none; width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-error\"><\/div>\n<\/div>\n<div class=\"mejs-overlay mejs-layer mejs-overlay-play\" style=\"width: 100%; height: 100%;\">\n<div class=\"mejs-overlay-button\" role=\"button\" tabindex=\"0\" aria-label=\"Play\" aria-pressed=\"false\"><\/div>\n<\/div>\n<\/div>\n<div class=\"mejs-controls\">\n<div class=\"mejs-button mejs-playpause-button mejs-play\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Play\" aria-label=\"Play\" tabindex=\"0\"><\/button><\/div>\n<div class=\"mejs-time mejs-currenttime-container\" role=\"timer\" aria-live=\"off\"><span class=\"mejs-currenttime\">00:00<\/span><\/div>\n<div class=\"mejs-time-rail\"><span class=\"mejs-time-total mejs-time-slider\" role=\"slider\" tabindex=\"0\" aria-label=\"Time Slider\" aria-valuemin=\"0\" aria-valuemax=\"0\" aria-valuenow=\"0\" aria-valuetext=\"00:00\"><span class=\"mejs-time-buffering\" style=\"display: none;\"><\/span><span class=\"mejs-time-loaded\"><\/span><span class=\"mejs-time-current\"><\/span><span class=\"mejs-time-hovered no-hover\"><\/span><span class=\"mejs-time-handle\"><span class=\"mejs-time-handle-content\"><\/span><\/span><span class=\"mejs-time-float\"><span class=\"mejs-time-float-current\">00:00<\/span><span class=\"mejs-time-float-corner\"><\/span><\/span><\/span><\/div>\n<div class=\"mejs-time mejs-duration-container\"><span class=\"mejs-duration\">00:00<\/span><\/div>\n<div class=\"mejs-button mejs-volume-button mejs-mute\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Mute\" aria-label=\"Mute\" tabindex=\"0\"><\/button><a href=\"javascript:void(0);\" class=\"mejs-volume-slider\" aria-label=\"Volume Slider\" aria-valuemin=\"0\" aria-valuemax=\"100\" role=\"slider\" aria-orientation=\"vertical\"><span class=\"mejs-offscreen\">Use Up\/Down Arrow keys to increase or decrease volume.<\/span><\/p>\n<div class=\"mejs-volume-total\">\n<div class=\"mejs-volume-current\" style=\"bottom: 0px; height: 100%;\"><\/div>\n<div class=\"mejs-volume-handle\" style=\"bottom: 100%; margin-bottom: -3px;\"><\/div>\n<\/div>\n<p><\/a><\/div>\n<div class=\"mejs-button mejs-fullscreen-button\"><button type=\"button\" aria-controls=\"mep_0\" title=\"Fullscreen\" aria-label=\"Fullscreen\" tabindex=\"0\"><\/button><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div dir=\"ltr\" style=\"text-align: left\">\n<h3><span dir=\"auto\" style=\"vertical-align: inherit\">Installation Guide<\/span><\/h3>\n<p><span dir=\"auto\" style=\"vertical-align: inherit\">After Extract, view with your favorite player.<\/span><\/p>\n<p><span dir=\"auto\" style=\"vertical-align: inherit\">Subtitles: None<\/span><\/p>\n<p><span dir=\"auto\" style=\"vertical-align: inherit\">Quality: 1080p<\/span><\/p>\n<\/div>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Download link<\/span><\/h3>\n<h4 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">Downloadly<\/span><\/h4>\n<p dir=\"ltr\" style=\"text-align: left\"><a href=\"https:\/\/dl4.downloadly.ir\/Files\/Elearning\/Udemy_FPGA101_Digital_System_Design_using_Verilog_and_Python_2025-9_Downloadly.ir.rar?nocache=1786176042\"><span dir=\"auto\" style=\"vertical-align: inherit\">Download file \u2013 945 MB<\/span><\/a><\/p>\n<h4 dir=\"ltr\">Rapidgator link<\/h4>\n<p><a href=\"https:\/\/rapidgator.net\/file\/a03e79c71f963248ab883ba1caf7e0c4\/Udemy_FPGA101_Digital_System_Design_using_Verilog_and_Python_2025-9_Downloadly.ir.rar.html\" target=\"_blank\" rel=\"noopener\">Download File \u2013 945 MB<\/a><\/p>\n<p dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">File(s) password: www.downloadly.ir<\/span><\/p>\n<h3 dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">File size<\/span><\/h3>\n<p dir=\"ltr\" style=\"text-align: left\"><span dir=\"auto\" style=\"vertical-align: inherit\">945 MB<\/span><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Description FPGA101: Digital System Design using Verilog and Python. This course teaches the fundamentals of digital system design using Verilog, implementing c<\/p>\n","protected":false},"author":1,"template":"","dgi_category":[10458],"dgi_tag":[111218,111219,111220,111221,111222,111223],"class_list":["post-13598","digital_item","type-digital_item","status-publish","has-post-thumbnail","hentry","dgi_category-video-tutorials","dgi_tag-course-fpga101-digital-system-design-using-verilog-and-python","dgi_tag-download-course-fpga101-digital-system-design-using-verilog-and-python","dgi_tag-download-fpga101-digital-system-design-using-verilog-and-python","dgi_tag-erwin-ouyang","dgi_tag-free-download-fpga101-digital-system-design-using-verilog-and-python","dgi_tag-free-fpga101-digital-system-design-using-verilog-and-python"],"_links":{"self":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/13598","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item"}],"about":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/types\/digital_item"}],"author":[{"embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"version-history":[{"count":0,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/digital_item\/13598\/revisions"}],"wp:attachment":[{"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/media?parent=13598"}],"wp:term":[{"taxonomy":"dgi_category","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_category?post=13598"},{"taxonomy":"dgi_tag","embeddable":true,"href":"https:\/\/nokobox.com\/index.php\/wp-json\/wp\/v2\/dgi_tag?post=13598"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}