Description
IP Verification using System Verilog (SV) with Project Demo course. This course is designed for beginners to experts. The content of this System Verilog course is structured in such a way that participants can learn and practice the modules in a few weeks.
During the course, various example codes are explained and a number of applications are simulated in industry standard simulators. Also, an example protocol is selected and testbench code is developed for it and test cases are written for the project. The assignments provided help the participants to practice writing the code and use it to develop the test bench and test cases.
What you will learn
- IP Verification Concepts
- Learning System Verilog language for Verification
- Develop test bench and test cases based on System Verilog to verify a specific IP
- A case study: How to verify an IP using SV
This course is suitable for people who:
- Internship for BE/MTech (ECE, EEE) students
- Engineers who are new to System Verilog.
Course details: IP Verification using System Verilog (SV) with Project Demo
- Publisher : Udemy
- Teacher : VLSI Mentor
- Language: English
- Level : Expert
- Lectures : 12
- Duration : 18 hours and 40 minutes
Course syllabus
Course prerequisites
- Digital fundamentals
- Verilog language
- Basics of Verification
- Linux commands
Course images
Sample course video
Installation Guide
After Extract, view with your favorite player.
Subtitles: English
Quality: 1080p
The 2025/7 version has the duration decreased by 1 minutes compared to 2024/11.
Download link
File(s) password: www.downloadly.ir
File size
11.93 GB
