Udemy – ASIC Design Verification using SV-UVM + Project Demo 2025-7

Updated August 10, 2026 5.19 GB

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Descriptions

ASIC Design Verification using SV-UVM + Project Demo, This course covers the basics of UVM methodology, components, objects, UVM Factory, configuration, phases, and reports. It follows a step-by-step approach to building a testbench using driver, sequencer, agent, environment, test, and top testbench. You will learn to build sequences for verifying the features of an example IP, develop UVM testbenches and test cases from scratch, and simulate them using a provided simulator. The course also demonstrates creating an example testbench, writing test cases, and running simulations.

It is designed for students pursuing BE/BTech/MTech in Electronics and Communication who want to learn UVM or do internships, as well as graduates who wish to simulate with free tools like EDA Playground. This complete course includes a project demonstration and assignments to make UVM learning easier. The agenda covers UVM overview, components and objects, TLM, factory, configuration, phases, reports, sequencer, driver, agent, monitor, test, scoreboard, topology, and test sequences. By the end, you will be able to apply for semiconductor design verification roles with confidence.

What you’ll learn

Learning Universal Verification Methodology (UVM)
How UVM can be used to build a testbench for any digital IP
Developing test cases using SV UVM for a digital IP
How to simulate the SV UVM test case

Who this course is for

BE/BTech/ME/MTech in Electronics and Communication
Those wanting to learn advanced verification methodology for IP verification in ASIC development
Those who want to do internships in VLSI Design Verification
Applicants for ASIC Design Verification roles in semiconductor companies