Description
Synopsys StarRC is the industry-leading EDA tool for extracting resistor, capacitor, and inductor noise for SoC designs in analog and digital circuits, published by Synopsys. Synopsys StarRC™, the gold standard noise extraction solution, is a key component of Synopsys digital design and Synopsys custom design families. Synopsys StarRC provides a silicon-accurate, high-performance extraction solution for SoC, custom digital, analog/mixed-signal, memory, and 3DIC designs. The Synopsys StarRC solution provides physical effects modeling for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, and beyond.
Its seamless integration with industry-standard digital and custom implementation systems, physical verification timing, signal integrity, power, thermal and circuit simulation streams, offers unparalleled ease of use and productivity to accelerate design closure and signature verification.
Synopsys StarRC Features:
- Multi-core distributed processing
- Multi-corner simultaneous extraction
- Fast ECO extraction for ECO TAT reduction
- Clock inductance extraction
- Integration with Synopsys PrimeTime and Synopsys Fusion compiler for ECO TAT reduction
- Integration of Synopsys PrimeSim circuit simulation
- Integration of custom layout environment
- Physical implementation interface (GDSII, LEF/DEF, NDM)
- Virtual metal filler for accurate design capacitor
- Metal filler reuse for ECO TAT reduction
- Hierarchical layout vs. schematic (LVS) and advanced device parameter ADP extraction flow
- Active node extraction
- Automatic power grid extraction optimization (TARGET_PWRA)
- Transparent simulation settings
- Permission queuing
- Advanced mitigation features for simulation efficiency
System Requirements
• IBM® RS/6000® AIX® (64)
• x86 Red Hat® Enterprise Linux® (64)
• x86 SUSE® Linux (64)
Picture
Synopsys StarRC Installation guide
Follow the instructions in Readme.txt file.
Downloadly link
Synopsys StarRC 2025-6 Linux
File Size
3.3 GB
