Description
The Complete SystemVerilog For Digital Design and Synthesis course. This course teaches advanced concepts of the SystemVerilog language for digital design and hardware synthesis through the construction of a 32-bit RISC-V processor. This course is a completely practical and laboratory-based path to the modern world of silicon and hardware design. In this course, the SystemVerilog language, which is known as the industry’s most powerful language for describing and verifying hardware, is fully taught. In this course, the student does not only learn the structure and rules of the language, but also applies all the concepts learned in the form of a large and long-term project. This project involves the design, simulation and synthesis of a system on a chip (SoC) based on the RISC-V architecture. The training begins with a review of the RISC-V architecture and goes step by step through the datapath, controller unit and memory units. The implementation of the Open Bus Interface (OBI) and the integration of peripherals such as UART are among the outstanding features of this course. Students will learn how to write code that is not only fully synthesizeable but also fully capable of being simulated for FPGA and ASIC chips. Complex structures such as FIFO buffers, finite state machines (FSMs), and word-aligned memories are also taught in this course, so that at the end of the course, the student will have a professional project to present on their resume.
What you will learn
- Master the principles and fundamentals of SystemVerilog, including data types, operators, modules, interfaces, and advanced language features for digital design.
- Write synthesizable code in SystemVerilog following industry best practices to create reliable hardware designs for FPGAs and ASICs.
- Design and verify digital circuits from simple combinational logic to complex sequential systems using simulation and testbenches.
- Build complete digital systems through 20 hands-on, step-by-step experiments, from simple adders to a complete RISC-V-based system-on-chip (SoC).
- Troubleshoot and validate designs using automated test environments and simulation techniques to ensure correct hardware behavior.
- Use interfaces and modports in SystemVerilog to create clean hierarchical designs with simplified module connections.
- Understand the differences between simulation-only structures and synthesizable code to avoid common errors in hardware design.
- Implementing complex hardware structures such as arithmetic and logic units (ALUs), register files, and FIFO buffers.
- Professionally manage clock dividers, synchronous logic, and memory alignment.
This course is suitable for people who:
- University students taking courses in digital design, computer architecture, or VLSI and need to learn industry-standard hardware description languages.
- New graduates preparing to enter the job market and work in the field of FPGA design or ASIC design.
- Professional engineers working in hardware design who want to deepen their SystemVerilog knowledge and learn best practices for writing synthesizable code.
- Verilog users who want to migrate to SystemVerilog and become familiar with its advanced features such as interfaces, objects, and improved data types.
- Hardware engineers looking to gain hands-on experience building complete systems, from basic circuits to a RISC-V system-on-chip.
Course specifications The Complete SystemVerilog For Digital Design and Synthesis
- Publisher: Udemy
- Instructor: AIC LAB
- Training level: Beginner to advanced
- Training duration: 9 hours and 2 minutes
- Number of lessons: 207
Course syllabus
Prerequisites for The Complete SystemVerilog For Digital Design and Synthesis Course
- Basic knowledge of Digital Logic Design is required
- Understanding of binary numbers and Boolean algebra (working with 0s and 1s)
- Familiarity with basic logic gates (AND, OR, XOR, NOT)
- Knowledge of combinational circuits like multiplexers and decoders
- Understanding of sequential circuits including flip-flops and registers
- Basic concepts of finite state machines (FSM)
Course images
Sample course video
Installation Guide
After Extract, view with your favorite player.
Subtitles: English
Quality: 1080p
Changes:
Version 2026/3 compared to 2026/1 has increased by 16 lessons and 2 minutes in duration. English subtitles were also added to the course.
Download link
Downloadly
Rapidgator
File(s) password: www.downloadly.ir
File size
4.61 GB
